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1 kinetis l series the kinetis l series is the most scalable portfolio of ultra low- power, mixed-signal arm cortex-m0+ mcus in the industry. the portfolio includes 5 mcu families that offer a broad range of memory, peripheral and package options. kinetis l series families share common peripherals and pin- counts allowing developers to migrate easily within an mcu family or between mcu families to take advantage of more memory or feature integration. this scalability allows developers to standardize on the kinetis l series for their end product platforms, maximising hardware and software reuse and reducing time-to-market. features common to all kinetis l series families include: ? 48 mhz arm cortex-m0+ core ? high-speed 12/16-bit analog-to-digital converters ? 12-bit digital-to-analog converters for all series except for klx4 family ? high-speed analog comparators ? low-power touch sensing with wake-up on touch from reduced power states for all series except for klx4 family ? powerful timers for a broad range of applications including motor control ? low power focused serial communication interfaces such as low power uart, spi, i2c etc. ? single power supply: 1.71v - 3.6v with multiple low- power modes support single operation temperature: -40 ~ 105 c (exclude csp package) freescale semiconductor document number:kl05pb product brief rev. 2, 6/2012 kl04/kl05 product brief supports all kl04 and kl05 devices ? 2011C2012 freescale semiconductor, inc. preliminary general business information contents 1 kinetis l series ................................. ........................1 2 kl04/kl05 sub-family introduction ... ................... 3 3 block diagram ............................ .............................. 3 4 features ................................ ..................................... 6 5 power modes ............................. .............................. 17 6 revision history ......................... ............................ 19
kinetis l series mcu families combine the latest low-power innovations with precision mixed-signal capability and a broad range of communication, connectivity, and human-machine interface peripherals. each mcu family is supported by a market-leading enablement bundle from freescale and numerous arm 3rd party ecosystem partners. the kl0x family is the entry-point to the kinetis l series and is compatible with the 8-bit s08pt family. the kl1x/2x/3x/4x families are compatible with each other and their equivalent arm cortex-m4 kinetis k series families - k10/20/30/40. kl2x family kl1x family kl0x family kl3x family family program flash packages key features low power mixed signal usb segment lcd kl4x family 8-32kb 32-256kb 32-256kb 64-256kb 128-256kb 16-48pin 32-80pin 32-121pin 64-121pin 64-121pin figure 1. kinetis l series families of mcu portfolio all kinetis l series families include a powerful array of analog, communication and timing and control peripherals with the level of feature integration increasing with flash memory size and the pin count. features within the kinetis l series families include: ? core and architecture: ? arm cortex-m0+ core delivering 1.77 coremark/mhz from single-cycle access memories ? single-cycle access to i/o and critical peripherals: up to 50 percent faster than standard i/o, improves reaction time to external events allowing bit banging and software protocol emulation ? two-stage pipeline: reduced number of cycles per instruction (cpi), enabling faster branch instruction and isr entry ? excellent code density vs. 8-bit and 16-bit mcus - reduces flash size, system cost and power consumption ? optimized access to program memory: accesses on alternate cycles reduces power consumption ? 100 percent compatible with arm cortex-m0 and a subset arm cortex-m3/m4: reuse existing compilers and debug tools ? simplified architecture: 56 instructions and 17 registers enables easy programming and efficient packaging of 8/16/32-bit data in memory ? linear 4 gb address space removes the need for paging/banking, reducing software complexity ? arm third-party ecosystem support: software and tools to help minimize development time/cost ? micro trace buffer: lightweight trace solution allows fast bug identification and correction ? bme: bit manipulation engine reduces code size and cycles for bit oriented operations to peripheral registers eliminating traditional methods where the core would need to perform read-modify-write instructions. ? up to 4-channel dma for peripheral and memory servicing with minimal cpu intervention ? broad range of performance levels with cpu frequencies up to 48 mhz ? ultra low-power: ? next-generation 32-bit arm cortex m0+ core: 2x more coremark/ma than the closest 8/16-bit architecture kinetis l series kl04/kl05 product brief, rev. 2, 6/2012 2 preliminary freescale semiconductor, inc. general business information
? multiple flexible low-power modes, including new operation clocking option which reduces dynamic power by shutting off bus and system clocks for lowest power core processing. peripherals with an alternate asynchronous clock source can continue operation. ? uart, spi, i2c, adc, dac, tpm, lpt and dma support low-power mode operation without waking up the core ? memory: ? scalable memory footprints from 8 kb flash / 1 kb sram to 128 kb flash / 16 kb sram ? embedded 64 b cache memory for optimizing bus bandwidth and flash execution performance (feature not available on kl02 family) ? mixed-signal analog: ? fast, high precision 16-, or 12-bit adcs with optional differential pairs, 12-bit dacs, high speed comparators. powerful signal conditioning, conversion and analysis capability with reduced system cost ? human machine interface (hmi): ? optional capacitive touch sensing interface with full low-power support and minimal current adder when enabled ? connectivity and communications: ? all uarts support dma transfers, and can trigger when data on bus is detected, uart0 supports 4x to 32x over sampling ratio. asynchronous transmit and receive operation for operating in stop/vlps modes. ? up to two spis ? up to two iics ? full-speed usb otg controller with on-chip transceiver ? reliability, safety and security: ? internal watchdog ? timing and control: ? powerful timer modules which support general purpose, pwm, and motor control functions ? periodic interrupt timer for rtos task scheduler time base or trigger source for adc conversion and timer modules ? system: ? gpio with pin interrupt functionality ? wide operating voltage range from 1.71 v to 3.6 v with flash programmable down to 1.71 v with fully functional flash and analog peripherals ? ambient operating temperature ranges from -40 c to 105 c 2 kl04/kl05 sub-family introduction the device is highly-integrated, market leading ultra low power 32-bit microcontroller based on the enhanced cortex-m0+ (cm0+) core platform. the family derivatives feature: ? core platform clock up to 48 mhz, bus clock up to 24 mhz ? memory option is up to 32 kb flash and 4 kb ram ? wide operating voltage ranges from 1.71v to 3.6v with full functional flash program/erase/read operations ? multiple package options from 24-pin to 48-pin ? ambient operating temperature ranges from C40 c to 105 c the family acts as an ultra low power, cost effective microcontroller to provide developers an appropriate entry-level 32-bit solution. the family is next generation mcu solution for low cost, low power, high performance devices applications. its valuable for cost-sensitive, portable applications requiring long battery life-time. 3 block diagram the below figure shows a superset block diagram of the device. other devices within the family have a subset of the features. kl04/kl05 sub-family introduction kl04/kl05 product brief, rev. 2, 6/2012 freescale semiconductor, inc. preliminary 3 general business information
memories and memory interfaces program flash ram 6-bit dac watchdog analog timers communication interfaces security and integrity spi x1 low power timer clocks frequency- core debug interfaces interrupt controller comparator x1 analog human-machine interface (hmi) system dma internal watchdog locked loop reference internal clocks timers interrupt periodic oscillator low/high frequency low power uart x1 ? cortex?-m0+ arm with gpios interrupt bme mtb rtc internal kinetis kl04 family legend x1 i c 2 x1 timers 1x6ch+1x2ch 12-bit adc x1 figure 2. kl04 family block diagram block diagram kl04/kl05 product brief, rev. 2, 6/2012 4 preliminary freescale semiconductor, inc. general business information
memories and memory interfaces program flash ram 6-bit dac analog timers communication interfaces security and integrity spi x1 low power timer clocks frequency- core debug interfaces interrupt controller comparator x1 analog human-machine interface (hmi) system dma internal watchdog locked loop reference internal clocks timers interrupt periodic oscillator low/high frequency low power uart x1 ? cortex?-m0+ arm with gpios interrupt kinetis kl05 family legend x1 i c 2 x1 timers 1x6ch+1x2ch 12-bit adc x1 tsi 12-bit dac bme mtb rtc watchdog internal figure 3. kl05 family block diagram block diagram kl04/kl05 product brief, rev. 2, 6/2012 freescale semiconductor, inc. preliminary 5 general business information
features 4.1 feature summary all devices within the kl04 and kl05 family features the following at a minimum: table 1. common features among all kl04 and kl05 devices operating characteristics ? 1.71 v to 3.6 v ? temperature range (t a ) -40c to 105c ? flexible modes of operation core features ? next generation 32-bit arm cortex m0+ core ? support up to 32 interrupt request sources ? nested vectored interrupt controller (nvic) ? debug & trace capability ? 2-pin serial wire debug (swd) ? micro trace buffer (mtb) system and power management ? software watchdog ? integrated bit manipulation engine (bme) ? dma controller ? low-leakage wake-up unit (llwu) ? power management controller with 10 different power modes ? non-maskable interrupt (nmi) ? 80-bit unique identification (id) number per chip clocks ? external crystal oscillator or resonator ? dc- 48 mhz external square wave input clock ? internal clock references ? 31.25 to 39.063 khz oscillator ? 4 mhz oscillator ? 1 khz oscillator ? frequency-locked loop with the range of ? 20-25 mhz ? 40-48 mhz memory and memory interfaces ? up to 32 kb with 64 byte flash cache ? up to 4 kb random-access memory security and integrity ? cop watchdog analog ? 12-bit analog-to-digital converter( adc) ? high speed comparator (hscmp)with internal 6-bit digital-to-analog converter (dac) ? 12-bit digital-to-analog converter (dac) for kl05 timers ? one 6-channel and one 2-channel 16-bit tpm modules ? 32-bit programmable interrupt timer (pit) ? real-time clock (srtc) ? low-power timer (lptmr) ? system tick timer (systik) communications ? spi with dma support ? i 2 c with dma support ? low-power uart with dma support table continues on the next page... 4 features kl04/kl05 product brief, rev. 2, 6/2012 6 preliminary freescale semiconductor, inc. general business information
table 1. common features among all kl04 and kl05 devices (continued) human-machine interface ? gpio with pin interrupt support, dma request capability, and other pin control options ? capacitive touch sensing inputs for kl05 4.2 memory and package options the following table summarizes the memory and package options for the kl0x family. all devices which share a common package are pin-for-pin compatible. table 2. kl0x family summary sub-family performance (mhz) memory package flash (kb) sram (kb) 24 qfn (4x4) 32 lqfp (7x7) 32 qfn (5x5) 48 lqfp (7x7) 64 lqfp (10x10) 80 lqfp (12x12) 100 lqfp (14x14) kl04 48 8 1 + + + 48 16 2 + + + + 48 32 4 + + + + kl05 48 8 1 + + + 48 16 2 + + + + 48 32 4 + + + + 4.3 part numbers and packaging q kl## a fff t pp cc (n) qualification status family flash size temperature range (c) speed (mhz) package identifier tape and reel (t&r) key attribute figure 4. part numbers diagrams features kl04/kl05 product brief, rev. 2, 6/2012 freescale semiconductor, inc. preliminary 7 general business information
field description values q qualification status ? m = fully qualified, general market flow ? p = prequalification kl## kinetis family ? kl04 ? kl05 a key attribute ? z = cortex-m0+ fff program flash memory size ? 8 = 8 kb ? 16 = 16 kb ? 32 = 32 kb r silicon revision ? (blank) = main ? a = revision after main t temperature range (c) ? v = C40 to 105 pp package identifier ? fk = 24 qfn (4 mm x 4 mm) ? lc = 32 lqfp (7 mm x 7 mm) ? fm = 32 qfn (5 mm x 5 mm) ? lf = 48 lqfp (7 mm x 7 mm) cc maximum cpu frequency (mhz) ? 4 = 48 mhz n packaging type ? r = tape and reel ? (blank) = trays 4.4 kl04/kl05 family features the following sections list the differences among the various devices available within the kl04/kl05 family. the features listed below each part number specify the maximum configuration available on that device. the signal multiplexing configuration determines which modules can be used simultaneously. 4.4.1 kl04 family features (48mhz performance) table 3. kl04 48mhz performance table mc partnumber mkl04z8vfk4(r) MKL04Z16VFK4(r) mkl04z32vfk4(r) mkl04z8vlc4(r) mkl04z16vlc4(r) mkl04z32vlc4(r) mkl04z8vfm4(r) mkl04z16vfm4(r) mkl04z32vfm4(r) mkl04z16vlf4(r) mkl04z32vlf4(r) general cpu frequency 48 mhz 48 mhz 48 mhz 48 mhz 48 mhz 48 mhz 48 mhz 48 mhz 48 mhz 48 mhz 48 mhz pin count 24 24 24 32 32 32 32 32 32 48 48 package qfn qfn qfn lqfp lqfp lqfp qfn qfn qfn lqfp lqfp memories and memory interfaces flash 8kb 16kb 32kb 8kb 16kb 32kb 8kb 16kb 32kb 16kb 32kb table continues on the next page... features kl04/kl05 product brief, rev. 2, 6/2012 8 preliminary freescale semiconductor, inc. general business information
table 3. kl04 48mhz performance table (continued) mc partnumber mkl04z8vfk4(r) MKL04Z16VFK4(r) mkl04z32vfk4(r) mkl04z8vlc4(r) mkl04z16vlc4(r) mkl04z32vlc4(r) mkl04z8vfm4(r) mkl04z16vfm4(r) mkl04z32vfm4(r) mkl04z16vlf4(r) mkl04z32vlf4(r) sram 1kb 2kb 4kb 1kb 2kb 4kb 1kb 2kb 4kb 2kb 4kb cache 64b 64b 64b 64b 64b 64b 64b 64b 64b 64b 64b core modules debug swd swd swd swd swd swd swd swd swd swd swd trace mtb mtb mtb mtb mtb mtb mtb mtb mtb mtb mtb nmi yes yes yes yes yes yes yes yes yes yes yes system modules watchdog yes yes yes yes yes yes yes yes yes yes yes pmc yes yes yes yes yes yes yes yes yes yes yes dma 4ch 4ch 4ch 4ch 4ch 4ch 4ch 4ch 4ch 4ch 4ch clock modules mcg fll fll fll fll fll fll fll fll fll fll fll osc (32-40khz/3-32mhz) yes yes yes yes yes yes yes yes yes yes yes rtc yes yes yes yes yes yes yes yes yes yes yes analog total se channels sar adc (w temp sense) 12bit, 1x12ch 12bit, 1x12ch 12bit, 1x12ch 12bit, 1x14ch 12bit, 1x14ch 12bit, 1x14ch 12bit, 1x14ch 12bit, 1x14ch 12bit, 1x14ch 12bit, 1x14ch 12bit, 1x14ch dp channels - - - - - - - - - - - se channels 12ch 12ch 12ch 14ch 14ch 14ch 14ch 14ch 14ch 14ch 14ch 12-bit dac - - - - - - - - - - - analog comparator 1 1 1 1 1 1 1 1 1 1 1 analog comparator inputs 4 4 4 4 4 4 4 4 4 4 4 timers general purpose/pwm 1x6ch +1x2ch 1x6ch +1x2ch 1x6ch +1x2ch 1x6ch +1x2ch 1x6ch +1x2ch 1x6ch +1x2ch 1x6ch +1x2ch 1x6ch +1x2ch 1x6ch +1x2ch 1x6ch +1x2ch 1x6ch +1x2ch low power timer 1 1 1 1 1 1 1 1 1 1 1 pit (32bit) 1x2ch 1x2ch 1x2ch 1x2ch 1x2ch 1x2ch 1x2ch 1x2ch 1x2ch 1x2ch 1x2ch communication interfaces low power uart 1 1 1 1 1 1 1 1 1 1 1 uart - - - - - - - - - - - spi chip selects per module 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 i2c 1 1 1 1 1 1 1 1 1 1 1 usb otg ls/fs w/ on-chip xcvr - - - - - - - - - - - usb 120mareg - - - - - - - - - - - table continues on the next page... features kl04/kl05 product brief, rev. 2, 6/2012 freescale semiconductor, inc. preliminary 9 general business information
table 3. kl04 48mhz performance table (continued) mc partnumber mkl04z8vfk4(r) MKL04Z16VFK4(r) mkl04z32vfk4(r) mkl04z8vlc4(r) mkl04z16vlc4(r) mkl04z32vlc4(r) mkl04z8vfm4(r) mkl04z16vfm4(r) mkl04z32vfm4(r) mkl04z16vlf4(r) mkl04z32vlf4(r) human-machine interface segment lcd - - - - - - - - - - - tsi (capacitive touch) - - - - - - - - - - - total gpios 22 22 22 28 28 28 28 28 28 41 41 gpios w/ interrupt 12 12 12 14 14 14 14 14 14 18 18 high current gpios (18ma) 2 2 2 4 4 4 4 4 4 4 4 operating characteristics voltage range 1.71-3. 6v 1.71-3. 6v 1.71-3. 6v 1.71-3. 6v 1.71-3. 6v 1.71-3. 6v 1.71-3. 6v 1.71-3. 6v 1.71-3. 6v 1.71-3. 6v 1.71-3. 6v flash write v 1.71v 1.71v 1.71v 1.71v 1.71v 1.71v 1.71v 1.71v 1.71v 1.71v 1.71v temp range -40 to 105c -40 to 105c -40 to 105c -40 to 105c -40 to 105c -40 to 105c -40 to 105c -40 to 105c -40 to 105c -40 to 105c -40 to 105c 4.4.2 kl05 family features (48mhz performance) table 4. kl05 48mhz performance table mc partnumber mkl05z8vfk4(r) mkl05z16vfk4(r) mkl05z32vfk4(r) mkl05z8vlc4(r) mkl05z16vlc4(r) mkl05z32vlc4(r) mkl05z8vfm4(r) mkl05z16vfm4(r) mkl05z32vfm4(r) mkl05z16vlf4(r) mkl05z32vlf4(r) general cpu frequency 48 mhz 48 mhz 48 mhz 48 mhz 48 mhz 48 mhz 48 mhz 48 mhz 48 mhz 48 mhz 48 mhz pin count 24 24 24 32 32 32 32 32 32 48 48 package qfn qfn qfn lqfp lqfp lqfp qfn qfn qfn lqfp lqfp memories and memory interfaces flash 8kb 16kb 32kb 8kb 16kb 32kb 8kb 16kb 32kb 16kb 32kb sram 1kb 2kb 4kb 1kb 2kb 4kb 1kb 2kb 4kb 2kb 4kb cache 64b 64b 64b 64b 64b 64b 64b 64b 64b 64b 64b core modules debug swd swd swd swd swd swd swd swd swd swd swd table continues on the next page... features kl04/kl05 product brief, rev. 2, 6/2012 10 preliminary freescale semiconductor, inc. general business information
table 4. kl05 48mhz performance table (continued) mc partnumber mkl05z8vfk4(r) mkl05z16vfk4(r) mkl05z32vfk4(r) mkl05z8vlc4(r) mkl05z16vlc4(r) mkl05z32vlc4(r) mkl05z8vfm4(r) mkl05z16vfm4(r) mkl05z32vfm4(r) mkl05z16vlf4(r) mkl05z32vlf4(r) trace mtb mtb mtb mtb mtb mtb mtb mtb mtb mtb mtb nmi yes yes yes yes yes yes yes yes yes yes yes system modules watchdog yes yes yes yes yes yes yes yes yes yes yes pmc yes yes yes yes yes yes yes yes yes yes yes dma 4ch 4ch 4ch 4ch 4ch 4ch 4ch 4ch 4ch 4ch 4ch clock modules mcg fll fll fll fll fll fll fll fll fll fll fll osc (32-40khz/3-32mhz) yes yes yes yes yes yes yes yes yes yes yes rtc yes yes yes yes yes yes yes yes yes yes yes analog total se channels sar adc (w temp sense) 12bit, 1x12ch 12bit, 1x12ch 12bit, 1x12ch 12bit, 1x14ch 12bit, 1x14ch 12bit, 1x14ch 12bit, 1x14ch 12bit, 1x14ch 12bit, 1x14ch 12bit, 1x14ch 12bit, 1x14ch dp channels - - - - - - - - - - - se channels 12ch 12ch 12ch 14ch 14ch 14ch 14ch 14ch 14ch 14ch 14ch 12-bit dac 1 1 1 1 1 1 1 1 1 1 1 analog comparator 1 1 1 1 1 1 1 1 1 1 1 analog comparator inputs 4 4 4 4 4 4 4 4 4 4 4 timers general purpose/pwm 1x6ch +1x2ch 1x6ch +1x2ch 1x6ch +1x2ch 1x6ch +1x2ch 1x6ch +1x2ch 1x6ch +1x2ch 1x6ch +1x2ch 1x6ch +1x2ch 1x6ch +1x2ch 1x6ch +1x2ch 1x6ch +1x2ch low power timer 1 1 1 1 1 1 1 1 1 1 1 pit (32bit) 1x2ch 1x2ch 1x2ch 1x2ch 1x2ch 1x2ch 1x2ch 1x2ch 1x2ch 1x2ch 1x2ch communication interfaces low power uart 1 1 1 1 1 1 1 1 1 1 1 uart - - - - - - - - - - - spi chip selects per module 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 i2c 1 1 1 1 1 1 1 1 1 1 1 usb otg ls/fs w/ on-chip xcvr - - - - - - - - - - - usb 120mareg - - - - - - - - - - - human-machine interface segment lcd - - - - - - - - - - - tsi (capacitive touch) 8ch 8ch 8ch 12ch 12ch 12ch 12ch 12ch 12ch 12ch 12ch total gpios 22 22 22 28 28 28 28 28 28 41 41 table continues on the next page... features kl04/kl05 product brief, rev. 2, 6/2012 freescale semiconductor, inc. preliminary 11 general business information
table 4. kl05 48mhz performance table (continued) mc partnumber mkl05z8vfk4(r) mkl05z16vfk4(r) mkl05z32vfk4(r) mkl05z8vlc4(r) mkl05z16vlc4(r) mkl05z32vlc4(r) mkl05z8vfm4(r) mkl05z16vfm4(r) mkl05z32vfm4(r) mkl05z16vlf4(r) mkl05z32vlf4(r) gpios w/ interrupt 12 12 12 14 14 14 14 14 14 18 18 high current gpios (18ma) 2 2 2 4 4 4 4 4 4 4 4 operating characteristics voltage range 1.71-3. 6v 1.71-3. 6v 1.71-3. 6v 1.71-3. 6v 1.71-3. 6v 1.71-3. 6v 1.71-3. 6v 1.71-3. 6v 1.71-3. 6v 1.71-3. 6v 1.71-3. 6v flash write v 1.71v 1.71v 1.71v 1.71v 1.71v 1.71v 1.71v 1.71v 1.71v 1.71v 1.71v temp range -40 to 105c -40 to 105c -40 to 105c -40 to 105c -40 to 105c -40 to 105c -40 to 105c -40 to 105c -40 to 105c -40 to 105c -40 to 105c 4.5 module-by-module feature list the following sections describe the high-level module features for the family's superset device. see the previous section for differences among the subset devices. core modules 4.5.1.1 arm cortex m0+ core ? up to 48 mhz core frequency from 1.71 v to 3.6 v across temperature range of C40 c to 105 c ? support up to 32 interrupt request sources ? 2-stage pipeline microarchitecture for reduced power consumption and improved architectural performance (cycles per instruction) ? binary compatible instruction set architecture with the cm0 core ? thumb instruction set combines high code density with 32-bit performance ? serial wire debug (swd) reduces the number of pins required for debugging ? micro trace buffer (mtb) provides lightweight program trace capabilities using system ram as the destination memory ? single cycle 32 bits by 32 bits multiply 4.5.1.2 nested vectored interrupt controller (nvic) ? up to 32 interrupt sources ? includes a single non-maskable interrupt 4.5.1.3 wake-up interrupt controller (wic) ? supports interrupt handling when system clocking is disabled in low power modes 4.5.1 core modules kl04/kl05 product brief, rev. 2, 6/2012 12 preliminary freescale semiconductor, inc. general business information
? takes over and emulates the nvic behavior when correctly primed by the nvic on entry to very-deep-sleep ? a rudimentary interrupt masking system with no prioritization logic signals for wake-up as soon as a non-masked interrupt is detected ? contains no programmers model visible state and is therefore invisible to end users of the device other than through the benefits of reduced power consumption while sleeping 4.5.1.4 debug controller ? 2-pin serial wire debug (swd) provides external debugger interface ? micro trace buffer (mtb) provides simple execution trace capability and operates as a simple ahb-lite sram controller system modules 4.5.2.1 power management control unit (pmc) ? separate digital (regulated) and analog (referenced to digital) supply outputs ? programmable power saving modes ? no output supply decoupling capacitors required ? available wake-up from power saving modes via rtc and external inputs ? integrated power-on reset (por) ? integrated low voltage detect (lvd) with reset (brownout) capability ? selectable lvd trip points ? programmable low voltage warning (lvw) interrupt capability ? buffered bandgap reference voltage output ? factory programmed trim for bandgap and lvd ? 1 khz low power oscillator (lpo) 4.5.2.2 dma channel multiplexer (dma mux) ? 4 independently selectable dma channel routers ? 2 periodic trigger sources available ? each channel router can be assigned to 1 of 63 possible peripheral dma sources 4.5.2.3 dma controller four independently programmable dma controller channels provides the means to directly transfer data between system memory and i/o peripherals ? dma controller is capable of functioning in run, wait and stop modes of operation ? dual-address transfers via 32-bit master connection to the system bus ? data transfers in 8-, 16-, or 32-bit blocks ? continuous-mode or cycle-steal transfers from software or peripheral initiation 4.5.2.4 cop watchdog module ? independent clock source input (independent from cpu/bus clock) ? choice between two clock sources ? lpo oscillator ? bus clock 4.5.2 system modules kl04/kl05 product brief, rev. 2, 6/2012 freescale semiconductor, inc. preliminary 13 general business information
4.5.2.5 system clocks ? system oscillator (xosc) loop-control pierce oscillator; crystal or ceramic resonator range of 32 khz to 40 khz (low range mode) or 3-32 mhz (high range mode) ? multipurpose clock generator (mcg) ? frequency-locked loop (fll) controlled by internal or external reference ? 20mhz~40mhz fll output ? 40mhz~48mhz fll output ? internal reference clocks can be used as a clock source for other on-chip peripherals ? on-chip rc oscillator range of 31.25 khz to 39.0625 khz with 0.2% trim step and 1% accuracy across temperature range of 0 c to 70 c and 2% accuracy across full temperature range ? ultra low power 4 mhz irc memories and memory interfaces 4.5.3.1 on-chip memory ? 48 mhz performance devices ? up to 32 kb program flash memory ? up to 4 kb sram ? security circuitry to prevent unauthorized access to ram and flash contents analog 4.5.4.1 analog-to-digital converter (adc) ? linear successive approximation algorithm with up to 16-bit resolution ? output modes: ? single-ended 12-bit, 10-bit, and 8-bit modes, in right-justified unsigned format ? single or continuous conversion ? configurable sample time and conversion speed/power ? conversion complete and hardware average complete flag and interrupt ? input clock selectable from up to four sources ? operation in low power modes for lower noise operation ? asynchronous clock source for lower noise operation with option to output the clock ? selectable asynchronous hardware conversion trigger with hardware channel select ? automatic compare with interrupt for various programmable values ? temperature sensor ? hardware average function ? selectable voltage reference ? self-calibration mode 4.5.4.2 high-speed analog comparator (cmp) ? 6-bit dac programmable reference generator output ? up to five selectable comparator inputs; each input can be compared with any input by any polarity sequence ? selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output ? comparator output supports: ? sampled 4.5.3 4.5.4 memories and memory interfaces kl04/kl05 product brief, rev. 2, 6/2012 14 preliminary freescale semiconductor, inc. general business information
? windowed (ideal for certain pwm zero-crossing-detection applications ? digitally filtered using external sample signal or scaled peripheral clock ? two performance modes: ? shorter propagation delay at the expense of higher power ? low power, with longer propagation delay ? operational in all mcu power modes except for vlls0 4.5.4.3 12-bit digital-to-analog converter (dac) ? 12-bit resolution ? guaranteed 6-sigma monotonicity over input word ? high- and low-speed conversions ? 1 s conversion rate for high speed, 2 s for low speed ? power-down mode ? automatic mode allows the dac to generate its own output waveforms including square, triangle, and sawtooth ? automatic mode allows programmable period, update rate, and range ? dma support timers 4.5.5.1 timer/pwm (tpm) ? selectable source clock ? programmable prescaler ? 16-bit counter supporting free-running or initial/final value, and counting is up or up-down ? input capture, output compare, and edge-aligned and center-aligned pwm modes ? input capture and output compare modes ? generation of hardware triggers ? dma support for tpm events 4.5.5.2 periodic interrupt timers (pits) ? 2 general purpose interrupt timers ? 2 interrupt timers for triggering adc conversions ? 32-bit counter resolution ? clocked by bus clock frequency ? dma support 4.5.5.3 real-time clock (rtc) ? 32-bit seconds counter with 32-bit alarm ? 16-bit prescaler with compensation ? register write protection ? hard lock requires mcu por to enable write access ? soft lock requires system reset to enable write/read access 4.5.5 timers kl04/kl05 product brief, rev. 2, 6/2012 freescale semiconductor, inc. preliminary 15 general business information
communication interfaces 4.5.6.1 inter-integrated circuit (i 2 c) ? compatible with i 2 c bus standard and smbus specification version 2 features ? up to 100 kbps with maximum bus loading ? multi-master operation ? software programmable for one of 64 different serial clock frequencies ? programmable slave address and glitch input filter ? interrupt or dma driven byte-by-byte data transfer ? arbitration lost interrupt with automatic mode switching from master to slave ? calling address identification interrupt ? bus busy detection broadcast and 10-bit address extension ? address matching causes wake-up when processor is in low power mode 4.5.6.2 uart0 ? full-duplex operation ? standard mark/space non-return-to-zero (nrz) format ? 13-bit baud rate selection with fractional divide of 32 ? programmable 8-bit or 9-bit data format ? separately enabled transmitter and receiver ? programmable transmitter output polarity ? programmable receive input polarity ? 13-bit break character option ? 11-bit break character detection option ? two receiver wakeup methods: ? idle line wakeup ? address mark wakeup ? address match feature in receiver to reduce address mark wakeup isr overhead ? interrupt or dma driven operation ? receiver framing error detection ? hardware parity generation and checking ? configurable oversampling ratio to support from 1/4 to 1/32 bit-time noise detection ? operation in low power modes 4.5.6.3 serial peripheral interface (spi) ? master and slave mode ? full-duplex, three-wire synchronous transfers ? programmable transmit bit rate ? double-buffered transmit and receive data registers ? serial clock phase and polarity options ? slave select output ? mode fault error flag with cpu interrupt capability ? control of spi operation during wait mode ? selectable msb-first or lsb-first shifting ? support for both transmit and receive by dma 4.5.6 communication interfaces kl04/kl05 product brief, rev. 2, 6/2012 16 preliminary freescale semiconductor, inc. general business information
human machine interface 4.5.7.1 general purpose input/output (gpio) ? hysteresis and configurable pull up device on all input pins ? configurable drive strength on some output pins ? independent pin value register to read logic level on digital pin 4.5.7.2 touch sensor input (tsi) ? support up to 16 external electrodes ? automatic detection of electrode capacitance across all operational power modes ? internal reference oscillator for high-accuracy measurement ? configurable software or hardware scan trigger ? fully support freescale touch sensing software (tss) library ? capability to wake mcu from low power modes ? compensate for temperature and supply voltage variations ? high sensitivity change with 16-bit resolution register ? configurable up to 4096 scan times. ? support dma data transfer 5 power modes the power management controller (pmc) provides multiple power options to allow the user to optimize power consumption for the level of functionality needed. depending on the stop requirements of the user application, a variety of stop modes are available that provide state retention, partial power down or full power down of certain logic and/or memory. i/o states are held in all modes of operation. the following table compares the various power modes available. for each run mode there is a corresponding wait and stop mode. wait modes are similar to arm sleep modes. stop modes (vlps, stop) are similar to arm sleep deep mode. the very low power run (vlpr) operating mode can drastically reduce runtime power when the maximum bus frequency is not required to handle the application needs. the three primary modes of operation are run, wait and stop. the wfi instruction invokes both wait and stop modes for the chip. the primary modes are augmented in a number of ways to provide lower power based on application needs. table 5. chip power modes chip mode description core mode normal recovery method normal run allows maximum performance of chip. default mode out of reset; on- chip voltage regulator is on. run normal wait - via wfi allows peripherals to function while the core is in sleep mode, reducing power. nvic remains sensitive to interrupts; peripherals continue to be clocked. sleep interrupt normal stop - via wfi places chip in static state. lowest power mode that retains all registers while maintaining lvd protection. nvic is disabled; awic is used to wake up from interrupt; peripheral clocks are stopped. sleep deep interrupt table continues on the next page... 4.5.7 human machine interface kl04/kl05 product brief, rev. 2, 6/2012 freescale semiconductor, inc. preliminary 17 general business information
table 5. chip power modes (continued) chip mode description core mode normal recovery method vlpr (very low power run) on-chip voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. reduced frequency flash access mode (1 mhz); lvd off; in blpi clock mode, the fast internal reference oscillator is available to provide a low power nominal 4mhz source for the core with the nominal bus and flash clock required to be <800khz; alternatively, blpe clock mode can be used with an external clock or the crystal oscillator providing the clock source. run vlpw (very low power wait) -via wfi same as vlpr but with the core in sleep mode to further reduce power; nvic remains sensitive to interrupts (fclk = on). on-chip voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. sleep interrupt vlps (very low power stop)-via wfi places chip in static state with lvd operation off. lowest power mode with adc and pin interrupts functional. peripheral clocks are stopped, but osc, lptmr, rtc, cmp, tsi can be used. tpm and uart can optionally be enabled if their clock source is enabled. nvic is disabled (fclk = off); awic is used to wake up from interrupt. on-chip voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. all sram is operating (content retained and i/o states held). sleep deep interrupt lls (low leakage stop) state retention power mode. most peripherals are in state retention mode (with clocks stopped), but osc, llwu, lptmr, rtc, cmp,, tsi can be used. nvic is disabled; llwu is used to wake up. note: the llwu interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an lls recovery. all sram is operating (content retained and i/o states held). sleep deep wakeup interrupt 1 vlls3 (very low leakage stop3) most peripherals are disabled (with clocks stopped), but osc, llwu, lptmr, rtc, cmp, tsi can be used. nvic is disabled; llwu is used to wake up. sram_u and sram_l remain powered on (content retained and i/o states held). sleep deep wakeup reset 2 vlls1 (very low leakage stop1) most peripherals are disabled (with clocks stopped), but osc, llwu, lptmr, rtc, cmp, tsi can be used. nvic is disabled; llwu is used to wake up. all of sram_u and sram_l are powered off. sleep deep wakeup reset 2 vlls0 (very low leakage stop 0) most peripherals are disabled (with clocks stopped), but llwu, lptmr, rtc, tsi can be used. nvic is disabled; llwu is used to wake up. all of sram_u and sram_l are powered off. lpo shut down, optional por brown-out detection sleep deep wakeup reset 2 1. resumes normal run mode operation by executing the llwu interrupt service routine. 2. follows the reset flow with the llwu interrupt flag set for the nvic. power modes kl04/kl05 product brief, rev. 2, 6/2012 18 preliminary freescale semiconductor, inc. general business information
6 revision history the following table provides a revision history for this document. table 6. revision history rev. no. date substantial changes 1 3/16/2012 initial publish 2 6/4/2012 updated kinetis kl series of mcu portfolio diagram. updated kl04 family block diagram. updated adc feature for kl04. updated kl0x family summary table. revision history kl04/kl05 product brief, rev. 2, 6/2012 freescale semiconductor, inc. preliminary 19 general business information
how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com document number: kl05pb rev. 2, 6/2012 preliminary general business information information in this document is provided solely to enable system and software implementers to use freescale semiconductors products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "typical" parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals", must be validated for each customer application by customer's technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claims alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as their non-rohs-complaint and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale's environmental products program, go to http://www.freescale.com/epp. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2011C2012 freescale semiconductor, inc.

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